#ChipScope Core Inserter Project File Version 3.0
#Mon Sep 21 16:28:27 CST 2015
Project.device.designInputFile=C\:\\AllFile\\vast_work\\VSS_L9\\Design\\SYS_L9\\FPGA\\MainController\\VG803_D08_X17_udp\\VG803_D08_cs.ngc
Project.device.designOutputFile=C\:\\AllFile\\vast_work\\VSS_L9\\Design\\SYS_L9\\FPGA\\MainController\\VG803_D08_X17_udp\\VG803_D08_cs.ngc
Project.device.deviceFamily=15
Project.device.enableRPMs=true
Project.device.outputDirectory=C\:\\AllFile\\vast_work\\VSS_L9\\Design\\SYS_L9\\FPGA\\MainController\\VG803_D08_X17_udp\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=10
Project.filter<0>=*col_max*
Project.filter<1>=
Project.filter<2>=*dout_a*
Project.filter<3>=*col_count*
Project.filter<4>=*d_flag_a*
Project.filter<5>=*clk_out*
Project.filter<6>=*sys_clk_temp*
Project.filter<7>=*CLK0_OUT*
Project.filter<8>=*c0*
Project.filter<9>=*c0
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=clk_out<0>
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=s2_fpga gmii_dis_trans d_flag_a
Project.unit<0>.dataChannel<10>=s2_fpga gmii_dis_trans col_count<10>
Project.unit<0>.dataChannel<11>=s2_fpga gmii_dis_trans col_count<11>
Project.unit<0>.dataChannel<12>=s2_fpga gmii_dis_trans col_count<0>
Project.unit<0>.dataChannel<13>=s2_fpga gmii_dis_trans col_count<1>
Project.unit<0>.dataChannel<14>=s2_fpga gmii_dis_trans dout_a<0>
Project.unit<0>.dataChannel<15>=s2_fpga gmii_dis_trans dout_a<1>
Project.unit<0>.dataChannel<16>=s2_fpga gmii_dis_trans dout_a<2>
Project.unit<0>.dataChannel<17>=s2_fpga gmii_dis_trans dout_a<3>
Project.unit<0>.dataChannel<18>=s2_fpga gmii_dis_trans dout_a<4>
Project.unit<0>.dataChannel<19>=s2_fpga gmii_dis_trans dout_a<5>
Project.unit<0>.dataChannel<1>=s2_fpga gmii_dis_trans col_count<1>
Project.unit<0>.dataChannel<20>=s2_fpga gmii_dis_trans dout_a<6>
Project.unit<0>.dataChannel<21>=s2_fpga gmii_dis_trans dout_a<7>
Project.unit<0>.dataChannel<22>=s2_fpga gmii_dis_trans col_max<0>
Project.unit<0>.dataChannel<23>=s2_fpga gmii_dis_trans col_max<1>
Project.unit<0>.dataChannel<24>=s2_fpga gmii_dis_trans col_max<2>
Project.unit<0>.dataChannel<25>=s2_fpga gmii_dis_trans col_max<3>
Project.unit<0>.dataChannel<26>=s2_fpga gmii_dis_trans col_max<4>
Project.unit<0>.dataChannel<27>=s2_fpga gmii_dis_trans col_max<5>
Project.unit<0>.dataChannel<28>=s2_fpga gmii_dis_trans col_max<6>
Project.unit<0>.dataChannel<29>=s2_fpga gmii_dis_trans col_max<7>
Project.unit<0>.dataChannel<2>=s2_fpga gmii_dis_trans col_count<2>
Project.unit<0>.dataChannel<30>=s2_fpga gmii_dis_trans col_max<8>
Project.unit<0>.dataChannel<31>=s2_fpga gmii_dis_trans col_max<9>
Project.unit<0>.dataChannel<32>=s2_fpga gmii_dis_trans col_max<10>
Project.unit<0>.dataChannel<33>=s2_fpga gmii_dis_trans col_max<11>
Project.unit<0>.dataChannel<34>=s2_fpga gmii_dis_trans col_max<12>
Project.unit<0>.dataChannel<3>=s2_fpga gmii_dis_trans col_count<3>
Project.unit<0>.dataChannel<4>=s2_fpga gmii_dis_trans col_count<4>
Project.unit<0>.dataChannel<5>=s2_fpga gmii_dis_trans col_count<5>
Project.unit<0>.dataChannel<6>=s2_fpga gmii_dis_trans col_count<6>
Project.unit<0>.dataChannel<7>=s2_fpga gmii_dis_trans col_count<7>
Project.unit<0>.dataChannel<8>=s2_fpga gmii_dis_trans col_count<8>
Project.unit<0>.dataChannel<9>=s2_fpga gmii_dis_trans col_count<9>
Project.unit<0>.dataDepth=1024
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=35
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=s2_fpga gmii_dis_trans d_flag_a
Project.unit<0>.triggerChannel<1><0>=s2_fpga gmii_dis_trans col_count<1>
Project.unit<0>.triggerChannel<1><10>=s2_fpga gmii_dis_trans col_count<11>
Project.unit<0>.triggerChannel<1><11>=s2_fpga gmii_dis_trans col_count<0>
Project.unit<0>.triggerChannel<1><12>=s2_fpga gmii_dis_trans col_count<1>
Project.unit<0>.triggerChannel<1><1>=s2_fpga gmii_dis_trans col_count<2>
Project.unit<0>.triggerChannel<1><2>=s2_fpga gmii_dis_trans col_count<3>
Project.unit<0>.triggerChannel<1><3>=s2_fpga gmii_dis_trans col_count<4>
Project.unit<0>.triggerChannel<1><4>=s2_fpga gmii_dis_trans col_count<5>
Project.unit<0>.triggerChannel<1><5>=s2_fpga gmii_dis_trans col_count<6>
Project.unit<0>.triggerChannel<1><6>=s2_fpga gmii_dis_trans col_count<7>
Project.unit<0>.triggerChannel<1><7>=s2_fpga gmii_dis_trans col_count<8>
Project.unit<0>.triggerChannel<1><8>=s2_fpga gmii_dis_trans col_count<9>
Project.unit<0>.triggerChannel<1><9>=s2_fpga gmii_dis_trans col_count<10>
Project.unit<0>.triggerChannel<2><0>=s2_fpga gmii_dis_trans dout_a<0>
Project.unit<0>.triggerChannel<2><1>=s2_fpga gmii_dis_trans dout_a<1>
Project.unit<0>.triggerChannel<2><2>=s2_fpga gmii_dis_trans dout_a<2>
Project.unit<0>.triggerChannel<2><3>=s2_fpga gmii_dis_trans dout_a<3>
Project.unit<0>.triggerChannel<2><4>=s2_fpga gmii_dis_trans dout_a<4>
Project.unit<0>.triggerChannel<2><5>=s2_fpga gmii_dis_trans dout_a<5>
Project.unit<0>.triggerChannel<2><6>=s2_fpga gmii_dis_trans dout_a<6>
Project.unit<0>.triggerChannel<2><7>=s2_fpga gmii_dis_trans dout_a<7>
Project.unit<0>.triggerChannel<3><0>=s2_fpga gmii_dis_trans col_max<0>
Project.unit<0>.triggerChannel<3><10>=s2_fpga gmii_dis_trans col_max<10>
Project.unit<0>.triggerChannel<3><11>=s2_fpga gmii_dis_trans col_max<11>
Project.unit<0>.triggerChannel<3><12>=s2_fpga gmii_dis_trans col_max<12>
Project.unit<0>.triggerChannel<3><1>=s2_fpga gmii_dis_trans col_max<1>
Project.unit<0>.triggerChannel<3><2>=s2_fpga gmii_dis_trans col_max<2>
Project.unit<0>.triggerChannel<3><3>=s2_fpga gmii_dis_trans col_max<3>
Project.unit<0>.triggerChannel<3><4>=s2_fpga gmii_dis_trans col_max<4>
Project.unit<0>.triggerChannel<3><5>=s2_fpga gmii_dis_trans col_max<5>
Project.unit<0>.triggerChannel<3><6>=s2_fpga gmii_dis_trans col_max<6>
Project.unit<0>.triggerChannel<3><7>=s2_fpga gmii_dis_trans col_max<7>
Project.unit<0>.triggerChannel<3><8>=s2_fpga gmii_dis_trans col_max<8>
Project.unit<0>.triggerChannel<3><9>=s2_fpga gmii_dis_trans col_max<9>
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCount<1>=1
Project.unit<0>.triggerMatchCount<2>=1
Project.unit<0>.triggerMatchCount<3>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchCountWidth<1><0>=0
Project.unit<0>.triggerMatchCountWidth<2><0>=0
Project.unit<0>.triggerMatchCountWidth<3><0>=0
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerMatchType<1><0>=1
Project.unit<0>.triggerMatchType<2><0>=1
Project.unit<0>.triggerMatchType<3><0>=1
Project.unit<0>.triggerPortCount=4
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortIsData<1>=true
Project.unit<0>.triggerPortIsData<2>=true
Project.unit<0>.triggerPortIsData<3>=true
Project.unit<0>.triggerPortWidth<0>=1
Project.unit<0>.triggerPortWidth<1>=13
Project.unit<0>.triggerPortWidth<2>=8
Project.unit<0>.triggerPortWidth<3>=13
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
